FPGAmaster

@FPGAmaster-wyc

主要做FPGA教学和项目分享，我对FPGA领域非常感兴趣,多年来一直在研究和学习各种FPGA知识与技能。我会在博客中分享学习FPGA所需要的理论知识、实用技巧与项目实践等内容,帮助广大FPGA爱好者更轻松地入门和提高。如果你对FPGA也感兴趣,欢迎关注我的博客,一起学习和交流。

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Following

Public Repos

Private Repos

Language Breakdown

Lines of code distribution across 22 owned repositories

1819.0M Total LOC

1,486,028,031 lines

81.7%

N/A

VHDL

190,923,417 lines

10.5%

N/A

Verilog

84,705,972 lines

4.7%

N/A

Assembly

19,865,221 lines

1.1%

N/A

SystemVerilog

12,842,082 lines

0.7%

N/A

Other

24,673,883 lines

1.4%

N/A

I-Shaped Developer

I-shaped

Specialist — deep expertise in C

VHDL

Verilog

Assembly

SystemVerilog

Collaboration Network

Global Impact visualization

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0 active collaborators

Repos

PRs

Growth

+18%

Top Collaborators

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Coding Streak

Contribution activity over the past year

3 days

Contributions

Commits

Pull Requests

Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun

Based on GitHub activity

Less

Followers 14

Bai Feng

@baifengbai

tommmy-A

@tommmy-A

wangwangyou

@wangwangyou

shanyinshuiyue

@shanyinshuiyue

hades841

@hades841

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Following

7 total

Alex Forencich

@alexforencich

Carles Fernandez

@carlesfernandez

Dr.W.X

@WangXuan95

Heart Yang

@heartyang520

Lei Wang

@LeiWang1999

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Synced via GitHub

Top Repositories

AgentCore-Light

一个可开源复用的桌面状态灯项目：用 **ESP32-S3 + WS2812 8灯环 + SSD1306 OLED** 显示 Codex 工作状态和 Token 百分比，希望大家一起来跟我完善这个项目。

12 5

C++

zc706_PS_PL

zc706实现PS PL数据交互，通过串口发送16个16进制数据，然后通过串口把独处的数据打印出来

7ev开发板，VCU开发，FPGA工程

用Git管理，vivado工程的模板文件夹和tcl脚本文件

2 0

Tcl

xenomai

zynq搭载xenomai实时操作系统，zc706

1 1

GEN_data_LVDS

使用p701开发板，用lvds1，产生红外地平议数据

1 0

Shell

Learning-Summary

记录在学习petalinux的时候整理的教程

1 0

Python

verilog_commonModule

verilog通用模块，一些平常经常调用的小模块

接受LVDS数据，并输出sof，eof，sol，eol

1 0

Verilog

Open Source Impact

Contributions to external projects

0 merged PRs

No external contributions found.